To achieve a pull-in operation for a phase locked loop circuit, hereinafter referred to simply as PLL circuit, it is generally known to change the oscillation frequency of a voltage controlled oscillator, hereinafter referred to simply as VCO, by applying a scanning voltage, such as a triangular voltage waveforms, to the control input terminal of the VCO. This scanning voltage causes the VCO to scan its oscillating frequencies from its upper to its lower limits. An example of such a scanning apparatus for causing pull-in of PLL circuits is disclosed in Japanese Patent Application Laid-Open No. 56-69334 (Japanese Patent Application No. 54-146213).
FIG. 1 is a circuit diagram of the prior art scanning circuit disclosed in the aforementioned Japanese Patent Application. In the circuit, numeral 10 designates a PLL circuit. This circuit includes a phase comparator 3 outputting a difference signal corresponding to the difference in phase and frequency between the output signal OUT of a voltage controlled oscillator 2 and the input singal IN. The difference signal is applied to the inverted, that is negative, input terminal of a loop filter 4 composed of a differential amplifier OP.sub.1, resistors R.sub.1 and R.sub.2, and a condenser C.sub.1. The output (A) of the loop filter 4 is applied to the VCO 2 which operates to change the oscillation frequency of the VCO in accordance with the level of the control voltage.
Numeral 20 designates a scanning apparatus for causing pull-in of the PLL. In the circuit 20, D.C. voltages V.sub.g and V.sub.h, each of a voltage level different from the other, are applied to the inverted input terminal of the loop filter 4 through selecting switches 5 and 6, respectively, and a resistor R.sub.3. To control the selecting switches 5 and 6, there is provided an R-S flip-flop 7 composed of three-input NOR gates G.sub.1 and G.sub.2. The outputs (E) and (F) of gates G.sub.1 and G.sub.2, control the selecting switches 5 and 6, respectively.
Scanning circuit 20 also includes level comparators 8 and 9 for determining the upper and lower levels of the voltage level to be applied to the control voltage terminal of the VCO 2, the voltage level being the output (A) of the loop filter 4 as mentioned above. A reference voltage V.sub.m sets the upper voltage level and is applied to the inverted input terminal of the comparator 8. A reference voltage V.sub.n sets the lower voltage level and is applied to the non-inverted, that is, the positive input terminal of the comparator 9. The output (A) of the loop filter 4 is applied to the non-inverted input terminal of comparator 8 and the inverted input terminal of the comparator. The outputs (D) and (C) of comparators 8 and 9 are applied to the gates G.sub.2 and G.sub.1 of the flip-flop 7, respectively, to set or reset the gates G.sub.2 and G.sub.1, respectively.
Numeral 11 denotes a lock detector, generating a signal (B). Signal (B) assumes a logic high level in response to a phase lock condition in which the phase of the input signal IN is locked to the phase of the output signal OUT of the VCO 2. The output signal (B) thus becomes a clear signal applied to the gates G.sub.1 and G.sub.2 of the flip-flop 7.
As is conventional, the higher the level of the control voltage (A) to the VCO 2, the higher its oscillation frequency. The electronic switches 5 and 6 are caused to be in their closed or ON state producing a conductive path for voltages V.sub.g and V.sub.h to the negative input terminal of loop filter 4 when the respective control inputs (E) and (F) are at their high levels. The switches 5 and 6 are in their open or OFF state when the respective control inputs (E) and (F) are at their low levels. The D.C. voltages V.sub.g and V.sub.h are selected such that V.sub.g &gt;V.sub.d &gt;V.sub.h, where V.sub.d is the voltage to be applied to the non-inverted or positive terminal of the loop filter 4, and represents the central value of the amplitude of the phase difference signal from the phase comparator 3, which is applied to the inverted input terminal of loop filter 4.
The operation of the circuit of FIG. 1 is explained hereinafter with reference to the waveforms shown in FIG. 2. In FIGS. 1 and 2 the same letter designates the same voltage or the same output. FIGS. 2(G) and 2(H) illustrate the ON-OFF switching operation of the switches 5 and 6, respectively. Up to the time t.sub.1, the outputs (E) and (F) of the flip-flop 7 are low and high, respectively. Therefore, switch 5 is in its OFF state while switch 6 is in its ON state. As a result, the voltage V.sub.h, lower than the D.C. voltage V.sub.d, is applied to the inverted input terminal of the loop filter 4 and the loop filter 4 functions as an integrator for integrating the differential input (V.sub.d -V.sub.h). The output (A) of the loop filter 4 is increased in accordance with the integration of the differential input causing the oscillation frequency of the VCO 2 to increase in accordance with the output (A).
At the time t.sub.1, the voltage of the integrated output (A) reaches the reference voltage V.sub.m of the comparator 8, so that the output (D) of the comparator 8 is changed to a high level as shown in FIG. 2(D). Therefore, the output of the flip-flop 7 changes state to change the state of switch 5 to its ON state and the state of switch 6 to its OFF state. As a result, the differential input to the loop filter 4 becomes (V.sub.d -V.sub.g), causing the integrated output (A) to be decreased since V.sub.d &lt;V.sub.g. Correspondingly, the oscillation frequency of VCO 2 is also decreased. In this time, t.sub.1 -t.sub.2, the voltage of the output (A) is lower than the reference voltage V.sub.m, so that the output of the comparator 8 returns to the low level instantaneously; but, this change does not affect the state of the flip-flop 7.
Therefore, the output (A) is continuously decreased until time t.sub.2 at which time the level of the output (A) reaches the reference voltage V.sub.n. At this point, the output (C) of the comparator 9 assumes a logic high level to invert the flip-flop 7. As a result, the switch 5 returns to its OFF state and the switch 6 returns to its ON state thereby once again causing the output (A) of the loop filter 4 to increase. As output (A) begins to increase, the output (C) of the comparator 9 changes almost instantaneously from its high level to its low level. However, the state of flip-flop 7 remains the same and is not inverted. At time t.sub.3, when the phase of the input signal IN is coincident with the phase of the output signal OUT of the VCO, the output (B) of the lock detector 11 changes to a logic high level causing both of the outputs (E) and (F) of the flip-flop 7 to assume a logic low level. This causes both switches 5 and 6 to assume their open or OFF states. The PLL circuit now operates in its normal phase locked state.
With the scanning apparatus of FIG. 1 for pull-in of a PLL circuit, the desired operation can be achieved only when the input signal has only a bright line spectrum of the true frequency component to be locked within the scanning frequency, and does not contain a so-called spurious component as another bright line spectrum, or where, even if a spurious component is included therein, the energy of the spurious component is much less than the energy of the true bright line spectrum. However, where the input signal includes a high energy level spurious component in addition to the true bright line spectrum, the PLL circuit may lock onto the spurious component during the scanning operation causing what is termed herein as a mislock. Once the PLL circuit has been pulled in to the spurious component, normal lock to the true bright line spectrum is impossible until the energy of the spurious component is reduced.
An example of an input signal which can cause mislock is the reproduction signal produced by a record disc pre-recorded with a music signal modulated by the pulse 4 code modulation system. The so-called eight to fourteen modulation system, hereinafter referred to simply as EFM system, is one such pulse code modulation system. The digital signal is recorded on the record disc with a format as shown in FIG. 3. As shown in FIG. 3, one frame is composed of a plurality of channel bits, for example, 588 channel bits. The eight bit data signal is converted into 14 channel bits by the EFM system in accordance with a predetermined conversion table (not shown), to which is added a justification bit of 3 channel bits to make one unit composed of 17 channel bits. The units are recorded in the NRZI form, such that a transition from a logic level H to a logic level L or vice versa occurs in response to a bit at level 1, but no reverse is made when the bit is 0.
At the beginning of the frame, there is recorded the frame synchronizing signal. This signal is the first channel bit and is set to 1. The second to eleventh channel bits are set to 0, the twelfth channel bit is set to 1, the thirteenth to the twenty-second bits are set to 0, and the twenty-third channel bit to 1. A control signal referenced to the frame synchronizing signal is positioned at a predetermined location within the 588 channel bits. Signals are coded within a frame such that a "0" level lasting not less than 2 bit times nor more than 10 bit times is always preceded by a "1" level on one side and followed by a "1" level on its other. Namely, the minimum reverse interval is set to be 3T, where T being a period of one channel bit, and the maximum reverse interval is set to be 11T as shown in FIG. 3. Further, the data coding is designed that, except at the beginning of a frame, a maximum reverse interval of 11T never immediately follows another maximum reverse interval of 11T. It should be noted that, whether the frame synchronizing signal is initiated from a positive reverse from L to H or a negative reverse from H to L is determined by the state of the preceding signal.
In the portion at which the signal becomes a fixed pattern, corresponding to a zero level signal which may occur during the so-called intervals between music and the lead-in and the lead-out portions located at the outermost and the innermost tracks of a record disc, the mcdulated signal due to the EFM system becomes a time series signal having a repetitive pattern of 7T, 3T, 7T such that the pattern repeats every 17T. The signal obtained by differentiating the modulated signal and then fully rectifying it, includes a spurious signal with a comparatively high energy at n/17 times the clock frequency, n being an integer, less the bright line spectrum of the clock frequency. The channel bit rate in this case is 4.3218 MHz, and one over seventeen thereof becomes about 254 KHz. Therefore, the signal received by the PLL circuit in the non-music portion as mentioned above includes the spurious signal with the comparatively high energy of 4.3218 MHz.+-.n.times.254 KHz (n is an integer) less the bright lines spectrum of 4.3218 MHz.
In the pull-in operation of the PLL circuit, if the lock operation is undesirably effected at the frequency of the spurious signal, it is impossible to correctly lock the true frequency until the spurious signal is eliminated. Namely, the PLL circuit does not correctly lock the true frequency until the signal of the non-music portion is received. Therefore, it is impossible to correctly decode data.